Current detection in power FETS has long been used in a number of applications for a variety of purposes. For example, current detection may be used to help control the power FET or other components of a system in which the power FET resides. In most power switching applications, overcurrent detection can help identify potentially dangerous situations where a power FET may be conducting more than a rated current. Accordingly, overcurrent detection is highly desirable in power applications in which power FETs are used.
A particular power switching application where overcurrent detection is particularly useful is in class D power amplifiers. A particular issue that occurs with class D power amplifiers is increasing current that builds with each switching cycle of the amplifier output stage under certain conditions. In a number of class D power amplifiers, overcurrent detection in the above situation is difficult because conventional overcurrent detectors have a cyclic speed in the range of 100-150 ns. Due to the closed loop delay in detecting overcurrent, potentially damaging situations may arise that are not detected by the overcurrent detector until too late.
To overcome the above problem, an integrated overcurrent (OC) detector and gate drive control may be provided that can operate in close loop in a much shorter time frame. The coordination between the overcurrent detection and the gate drive control can detect an overcurrent and shut down a switching half bridge typically in under 46 ns. This type of detection and control, drawn from worst case models in high temperature conditions, becomes very challenging in noisy environments. In particular, current detection of a high side switch and a switching half bridge in a noisy environment with approximately 40V PVDD with reverse recovery events on the order of 10 amps and lasting 20-30 ns becomes very challenging. In addition, the coordination of the overcurrent detection and gate drive control can be somewhat complicated and add cost to the circuitry.
Typically, current detection for a FET can be achieved by measuring a voltage drop across the FET output, or the drain-source node. When the FET is conducting, and current flows from the drain to the source, the measured voltage drop is proportional to the current. The voltage is detected for a current falling in a single direction so that the polarity of the voltage is always the same when detected by the overcurrent sensor. Because FETs in these applications often experience negative voltages across their outputs, the overcurrent detector described above only detects current conditions in half of the possible number of voltage measurement situations. These types of overcurrent detectors do not obtain any information or have any knowledge of other states of the FETs, such as when the FET output voltage is negative. In a half bridge switching design, the lack of knowledge about two out of the four possible states for the output voltages of the two transistors provides a challenge in these types of overcurrent detectors to be designed with a very fast closed loop response, which can be complicated and expensive in practice.
Because overcurrent detectors with an overall response time of 100-200 ns are typically used to reduce costs and complexity for overcurrent sensing, systems using such overcurrent detectors sometimes suffer from drawbacks in the detection of overcurrent events. Some of these drawbacks are notable in class D audio amplifiers, and include such overcurrent issues as overcurrent detection holes and creeping current values. These drawbacks are particularly noticeable in cycle by cycle control in high voltage applications. The overcurrent detection hole refers to instances of overcurrent events that fall in between the overcurrent detection intervals, so that overcurrent events occur without being sensed. The creeping load current value drawback relates to a differential current measure, where the load current creeps upward over a number of switching cycles due to a finite response of the OC detector. The results of these overcurrent detection drawbacks are collapsing power supplies and the use of more expensive, bulkier and higher saturation current value inductors. An illustration of the difficulty with creeping overcurrent values is shown in the graph of FIG. 2. As can be seen in this cycle by cycle control example, with a supply voltage of 40 volts, the amperage increases with each cycle far above a desired amperage level, such as about SA. Because the amperage reference is also adjusted higher, the overall overcurrent condition is not detected. Part of the difficulty in eliminating the creeping overcurrent value illustrated in the graph of FIG. 2 is that the closed loop cycle time for the overcurrent detector should be below approximately 50 ns, which is a difficult specification to obtain.
It would also be desirable to improve the speed of detection of an overcurrent detector in a switching half bridge. It would also be desirable to obtain an overcurrent detector that has a decreased close loop cycle time and provides robust performance in noisy environments for switching half bridges.